Register File Capacity Satisfaction during Scheduling

In code generation of DSP code for distributed register files architectures the register binding, if not treated properly, becomes a complex problem to be solved. This is also the case for high level synthesis of DSP circuits with limited number of registers. A better way to deal with register file capacity constraints is to alternate between register binding and scheduling in a way that a decision made in one prunes the search space for the other. In this paper we present a method to handle register file capacity constraints during scheduling together with tight resourceand timing constraints. The characteristics of the exact coloring of conflict graphs, representing the relative overlap of values lifetimes, are analyzed in order to identify the values that are a bottleneck for register binding, and serialize their productions and consumptions. This is done with pairs of values until it can be guaranteed that the register file capacity constraints will be satisfied. Experiments in the FACTS environment show that we efficiently obtain high quality schedules for DSP kernels and inner loops. Keywords— Code generation; High Level Synthesis; Scheduling; Register binding; Constraint analysis.